This patent relates to capacitive transducers, and more particularly to techniques for reducing surface charge build-up in capacitive transducers.
Transducers convert a general physical quantity (for example, acceleration, pressure, etc.) to quantities that can be processed by electronic circuits. In particular, capacitive transducers produce a change of capacitance, corresponding to the magnitude of the measured input signal. Readout circuits for capacitive transducers transform the capacitance change produced by the transducer to an electrical signal. In the process, the circuits apply voltage waveforms to the transducer electrodes.
A capacitive accelerometer, a capacitive transducer for measuring acceleration, includes a mechanical sensing element and a readout circuit. FIG. 1 illustrates an exemplary embodiment of a mechanical sensing element 100 of a capacitive accelerometer. In this embodiment, the mechanical sensing element 100 includes a mass 102 suspended between a first spring 104 and a second spring 106, a first electrode 110 and a second electrode 112. A proximal end of the mass 102 is coupled to the first spring 104 and a distal end of the mass 102 is coupled to the second spring 106. The first spring 104 has two ends; a first end coupled to the proximal end of the mass 102 and a second end coupled to a substrate. The second spring 106 has two ends; a first end coupled to the distal end of the mass 102 and a second end coupled to the substrate. A common electrode M is coupled to the mass 102 and moves with the mass 102 relative to the substrate. The first and second electrodes 110, 112 are stationary relative to the substrate. In this embodiment a positive reference voltage VS is applied to the first electrode 110 and the negative reference voltage −VS is applied to the second electrode 112. A first variable capacitor C1 is formed between the first electrode 110 and the common electrode M, and a second variable capacitor C2 is formed between the second electrode 112 and the common electrode M.
In this embodiment, when the system is at rest, there is a substantially equal nominal gap g0 between the first electrode 110 and the common electrode M and between the second electrode 112 and the common electrode M, creating substantially equal capacitances in the first variable capacitor C1 and the second variable capacitor C2. An input acceleration moves the mass 102 relative to the substrate which varies the gaps between the electrodes and varies the capacitance of the variable capacitors C1, C2. Acceleration in the direction of arrow 120 deflects the mass 102 a distance Δx that is proportional to the input acceleration. This movement of the mass 102 increases the distance between the first electrode 110 and the common electrode M to g0+Δx, and decreases the distance between the second electrode 112 and the common electrode M to g0−Δx, which changes the capacitance of capacitors C1 and C2. The capacitance C of variable capacitors C1 and C2 can be determined by:
                              C                      1            /            2                          =                                            ɛ              0                        ⁢            A                                              g              0                        ±                          Δ              ⁢                                                          ⁢              x                                                          (        1        )            where ∈0 is dielectric permittivity, A is the area of the capacitive plates (which extend into the paper), g0 is the nominal gap and Δx is the displacement due to the acceleration. The readout circuit determines the value of Δx based on the capacitance change in capacitors C1 and C2.
FIG. 2 is a schematic of an exemplary embodiment of a self-balancing capacitive bridge 200. The switched-capacitor implementation shown in FIG. 2 has the advantage of straightforward DC biasing of the input without the need for a high resistance path, as well as a stable and well-defined transfer function over process and temperature. It also provides a discrete-time output signal, which can be digitized directly by an analog-to-digital converter (ADC). FIG. 2 shows a single-ended embodiment of a self-balancing bridge.
The self-balancing bridge 200 includes a sensor core and a readout or interface circuit. The sensor core 210 represents a capacitive sensor element, for example the sensing element 100 shown in FIG. 1 or one of various other capacitive sensor elements known in the art. The sensor core 210 includes two variable capacitors, C1 and C2, sharing a common node M that is coupled to the output of the sensor core 210. The readout circuit includes a forward path that passes the output of the sensor core 210 through an integrator 222, which provides gain, to the output V0. In this embodiment, the integrator 222 includes an amplifier 224 with an integrating capacitor Ci. The self-balancing bridge 200 also includes a first feedback path 230 and a second feedback path 240 that feedback the output voltage Vo to the sensor core 210. The first feedback path 230 feeds back the output voltage Vo through a first inverting amplifier 232 to a first summing node 234. The first summing node 234 sums the inverted output voltage −V0 and inverted reference voltage −VS, and outputs the resulting voltage −VS−V0 to the first variable sensor capacitor C1. The second feedback path 240 feeds back the output voltage Vo through a second inverting amplifier 242 to a second summing node 244. The second summing node 244 sums the inverted output voltage −V0 and reference voltage VS, and outputs the resulting voltage VS−V0 to the second variable sensor capacitor C2.
The self-balancing bridge 200 tries to equalize the absolute charge on the two sensor capacitors, C1 and C2. Under these conditions the output voltage is proportional to the ratio between the difference and the sum of the measured capacitors:
                              V          o                =                              -                          V              S                                ⁢                                                    C                1                            -                              C                2                                                                    C                1                            +                              C                2                                                                        (        2        )            Measuring the above ratio is of interest for a variety of applications, acceleration sensors being only one particular example.
FIG. 3 shows the voltage waveforms across the bridge capacitors C1 and C2 of FIG. 2. It is apparent that both VC1, the voltage across capacitor C1, and VC2, the voltage across capacitor C2, have non-zero average values. It is well-known that applying voltage waveforms with non-zero average values across pairs of electrodes in a micro-machined transducer leads to a build-up of surface charge, which disturbs the operation of the system. One particular consequence of surface-charge build-up is a drift of the DC offset, which is an important parameter in a number of applications.
A second disadvantage of the readout circuit in FIG. 2 is that the signal is transferred to the input of the amplifier through a single signal line 212. It is also generally known that such “single-ended” implementations are susceptible to unwanted interference. Differential signaling is the standard solution to this problem as shown in FIG. 4.
FIG. 4 shows an exemplary embodiment of a differential self-balancing capacitive bridge system 400. The differential system 400 includes a sensing element 402, a dual forward path 410 and two dual feedback paths 420, 430. In the differential system 400, the transducer 402 is implemented as two separate cores, a first core CA and a second core CB. The first core CA includes variable capacitors C1A and C2A that share a common node coupled to the output of the first core CA. The second core CB includes variable capacitors C1B and C2B that share a common node coupled to the output of the second core CB. The corresponding capacitors of the two cores react to the input signal in a substantially identical way (i.e., C1A=C1B and C2A=C2B). However, the electrical signals processed by the two cores have opposite polarity. In such designs any external interference appears as a “common-mode” signal and is rejected by the readout circuit.
The forward path 410 takes the output signals from both cores of the sensing element 402, passes them through an integrator 412 and produces an output signal V0. The first feedback path 420 feeds back the output signal V0 to a first summing node 422. The first summing node 422 inverts the output signal and sums it with a positive reference voltage VS to generate a first summation signal −V0+VS, where voltage (−V0+VS)/2 is provided to capacitor C1A of the first core CA and voltage −(−V0+VS)/2 is provided to capacitor C1B of the second core CB. The second feedback path 430 feeds back the output signal V0 to a second summing node 432. The second summing node 432 inverts the output signal and sums it with the inverted reference voltage −VS to generate a second summation signal −V0−VS, where voltage (−V0−VS)/2 is provided to capacitor C2A of the first core CA and voltage −(−V0−VS)/2 is provided to capacitor C2B of the second core CB.
FIG. 5 shows the voltage waveforms across the bridge capacitors of the transducer core 402 for the differential system 400 in FIG. 4. It is once again apparent that the waveforms have a non-zero average value, hence the surface charging problem persists in the differential implementation as well.
It would be desirable to have a substantially zero average voltage across the electrodes in the transducer to reduce surface charge build-up which would reduce drift in DC offset.